In the prior art, small-scale logic circuits are mounted in power ICs and thus require no microfabrication process as in the case with memory or logic LSIs. However, in the field of power management for power ICs and the like, a self-correction process based on a CPU has recently been required to perform more sophisticated voltage monitoring and charging functions. This requires the mounting of large-scale logic circuits on power ICs.
In general, memory or logic LSIs comprise submicron MOS transistors having a channel length of 1 μm or shorter in order to further integration. Such a short-channel-type MOS transistor has a punch-through stopper layer formed therein in order to restrain punch-through between a source area and a drain area. A semiconductor integrated circuit device comprising a punch-through stopper layer is described in Japanese Patent Application Publication No. 61-190983.
Furthermore, Japanese Patent Application Publication No. 60-10780 describes a method for forming a punch-through stopper layer using an ion injection method, while Japanese Patent Application Publication No. 60-105277 describes a method for manufacturing a MOS transistor employing an LDD structure with a P pocket in order to reduce the concentration of electric fields in the vicinity of the drain area.
However, when a submicron MOS transistor comprising a punch-through stopper layer as described above is integrated on the same substrate with an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, and a diffusion resistor, if the analog CMOS transistor, high voltage-resistance MOS transistor, bipolar transistor, diode, and diffusion resistor also have a punch-through stopper layer formed therein, the accuracy of the threshold voltage of the analog CMOS transistor may decrease due to variations in the surface concentration of a diffusion layer of the punch-through stopper layer, or the high voltage-resistance MOS transistor may have a reduced voltage resistance.
It would therefore be desirable to provide a semiconductor integrated circuit device having a submicron CMOS transistor integrated on the same substrate with an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor, without degrading the characteristics of these components.
It would further be desirable to provide a method for manufacturing a semiconductor integrated circuit device allowing a submicron CMOS transistor to be mounted on the same substrate together with an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor without degrading the characteristics of these components.